Iceberg Quantum, Diraq Validate qLDPC Architecture on Silicon Spin Hardware

VERA Brief

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Iceberg Quantum and Diraq have validated a high-rate quantum error correction architecture on silicon spin-qubit hardware. This demonstration, using NVIDIA's CUDA-Q Logical platform, shows a path for efficient logical qubit implementation without extensive global wiring.

Key facts

• Iceberg Quantum and Diraq have successfully compiled and validated Iceberg's Pinnacle qLDPC architecture.
• The validation was performed on Diraq's silicon spin-qubit hardware using NVIDIA's CUDA-Q Logical framework.
• The approach allows for high-rate quantum low-density parity-check error correction on silicon spin hardware.
• Electron shuttling facilitates localized qubit routing, reducing the need for extensive global wiring.
• This approach supports 1,000 logical qubits with an estimated 150,000 physical qubits.